/****************************************************************************
 *
 * Copyright 2019 NXP Semiconductors All Rights Reserved.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing,
 * software distributed under the License is distributed on an
 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
 * either express or implied. See the License for the specific
 * language governing permissions and limitations under the License.
 *
 ****************************************************************************/
/****************************************************************************
 * os/arch/arm/src/imxrt/imxrt_lpi2c.c
 *
 *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
 *   Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/

/************************************************************************************
 * Included Files
 ************************************************************************************/

#include <tinyara/config.h>

#include <sys/types.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <semaphore.h>
#include <errno.h>
#include <debug.h>

#include <tinyara/arch.h>
#include <tinyara/irq.h>
#include <tinyara/clock.h>
#include <tinyara/semaphore.h>
#include <tinyara/i2c.h>

#include "chip/imxrt_pinmux.h"
#include "chip/imxrt_ccm.h"
#include "chip/imxrt_periphclks.h"

#include <arch/board/board.h>

#include "up_arch.h"

#include "imxrt_i2c.h"
#include "imxrt_gpio.h"

/* At least one I2C peripheral must be enabled */

#if defined(CONFIG_IMXRT_LPI2C1) || defined(CONFIG_IMXRT_LPI2C2) || \
	defined(CONFIG_IMXRT_LPI2C3) || defined(CONFIG_IMXRT_LPI2C4)

/************************************************************************************
 * Pre-processor Definitions
 ************************************************************************************/

/* Configuration ********************************************************************/
/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used.  Instead,
 * CPU-intensive polling will be used.
 */

/* Interrupt wait timeout in seconds and milliseconds */

#if !defined(CONFIG_IMXRT_I2CTIMEOSEC) && !defined(CONFIG_IMXRT_I2CTIMEOMS)
#define CONFIG_IMXRT_I2CTIMEOSEC 0
#define CONFIG_IMXRT_I2CTIMEOMS  500	/* Default is 500 milliseconds */
#elif !defined(CONFIG_IMXRT_I2CTIMEOSEC)
#define CONFIG_IMXRT_I2CTIMEOSEC 0	/* User provided milliseconds */
#elif !defined(CONFIG_IMXRT_I2CTIMEOMS)
#define CONFIG_IMXRT_I2CTIMEOMS  0	/* User provided seconds */
#endif

/* Interrupt wait time timeout in system timer ticks */

#ifndef CONFIG_IMXRT_I2CTIMEOTICKS
#define CONFIG_IMXRT_I2CTIMEOTICKS \
	(SEC2TICK(CONFIG_IMXRT_I2CTIMEOSEC) + MSEC2TICK(CONFIG_IMXRT_I2CTIMEOMS))
#endif

#ifndef CONFIG_IMXRT_I2C_DYNTIMEO_STARTSTOP
#define CONFIG_IMXRT_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_IMXRT_I2CTIMEOTICKS)
#endif

/* Debug ****************************************************************************/

/* I2C event trace logic.  NOTE:  trace uses the internal, non-standard, low-level
 * debug interface syslog() but does not require that any other debug
 * is enabled.
 */

#ifndef CONFIG_I2C_TRACE
#define imxrt_lpi2c_tracereset(p)
#define imxrt_lpi2c_tracenew(p, s)
#define imxrt_lpi2c_traceevent(p, e, a)
#define imxrt_lpi2c_tracedump(p)
#endif

#ifndef CONFIG_I2C_NTRACE
#define CONFIG_I2C_NTRACE 32
#endif

#ifdef CONFIG_I2C_SLAVE
#error I2C slave logic is not supported yet for IMXRT
#endif

#define LPI2C_MASTER    1
#define LPI2C_SLAVE     2

#define MKI2C_OUTPUT(p) (((p) & GPIO_PADMUX_MASK) | \
			 IOMUX_OPENDRAIN | IOMUX_DRIVE_33OHM | \
			 IOMUX_SLEW_SLOW | (5 << GPIO_ALT_SHIFT) | \
			 IOMUX_PULL_NONE | GPIO_OUTPUT_ONE)

#define MKI2C_INPUT(p) (((p) & GPIO_PADMUX_MASK) | \
			IOMUX_DRIVE_HIZ | IOMUX_SLEW_SLOW | \
			IOMUX_CMOS_INPUT | (5 << GPIO_ALT_SHIFT) | \
			IOMUX_PULL_NONE)

#undef i2cerr
#undef i2cinfo
#if defined(DEBUG_IMX_I2C)
#define i2cinfo(format, ...)   printf(format, ##__VA_ARGS__)
#define i2cerr(format, ...)   printf(format, ##__VA_ARGS__)
#else
#define i2cinfo(format, ...)
//#define nerr(format, ...)
#endif
#define i2cerr(format, ...)   printf(format, ##__VA_ARGS__)

/************************************************************************************
 * Private Types
 ************************************************************************************/

/* Interrupt state */

enum imxrt_intstate_e {
	INTSTATE_IDLE = 0,			/* No I2C activity */
	INTSTATE_WAITING,			/* Waiting for completion of interrupt activity */
	INTSTATE_DONE,				/* Interrupt activity complete */
};

/* Trace events */

enum imxrt_trace_e {
	I2CEVENT_NONE = 0,			/* No events have occurred with this status */
	I2CEVENT_SENDADDR,			/* Start/Master bit set and address sent, param = msgc */
	I2CEVENT_SENDBYTE,			/* Send byte, param = dcnt */
	I2CEVENT_RCVBYTE,			/* Read more dta, param = dcnt */
	I2CEVENT_NOSTART,			/* BTF on last byte with no restart, param = msgc */
	I2CEVENT_STARTRESTART,		/* Last byte sent, re-starting, param = msgc */
	I2CEVENT_STOP,				/* Last byte sten, send stop, param = 0 */
	I2CEVENT_ERROR				/* Error occurred, param = 0 */
};

/* Trace data */

struct imxrt_trace_s {
	uint32_t status;			/* I2C 32-bit SR2|SR1 status */
	uint32_t count;				/* Interrupt count when status change */
	enum imxrt_intstate_e event;	/* Last event that occurred with this status */
	uint32_t parm;				/* Parameter associated with the event */
	clock_t time;				/* First of event or first status */
};

/* I2C Device hardware configuration */

struct imxrt_lpi2c_config_s {
	uint32_t base;				/* LPI2C base address */
	uint16_t busy_idle;			/* LPI2C Bus Idle Timeout */
	uint8_t filtscl;			/* Glitch Filter for SCL pin */
	uint8_t filtsda;			/* Glitch Filter for SDA pin */
	uint32_t scl_pin;			/* GPIO configuration for SCL as SCL */
	uint32_t sda_pin;			/* GPIO configuration for SDA as SDA */
	uint8_t mode;				/* Master or Slave mode */
#ifndef CONFIG_I2C_POLLED
	uint32_t irq;				/* Event IRQ */
#endif
};

/* I2C Device Private Data */

struct imxrt_lpi2c_priv_s {
	const struct i2c_ops_s *ops;	/* Standard I2C operations */
	const struct imxrt_lpi2c_config_s *config;	/* Port configuration */
	int refs;					/* Referernce count */
	sem_t sem_excl;				/* Mutual exclusion semaphore */
#ifndef CONFIG_I2C_POLLED
	sem_t sem_isr;				/* Interrupt wait semaphore */
#endif
	volatile uint8_t intstate;	/* Interrupt handshake (see enum imxrt_intstate_e) */
	int address;				/* Address used in this instantiation */

	uint8_t msgc;				/* Message count */
	struct i2c_msg_s *msgv;		/* Message list */
	uint8_t *ptr;				/* Current message buffer */
	uint32_t frequency;			/* Current I2C frequency */
	int dcnt;					/* Current message length */
	uint16_t flags;				/* Current message flags */

	/* I2C trace support */

#ifdef CONFIG_I2C_TRACE
	int tndx;					/* Trace array index */
	clock_t start_time;			/* Time when the trace was started */

	/* The actual trace data */

	struct imxrt_trace_s trace[CONFIG_I2C_NTRACE];
#endif

	uint32_t status;			/* End of transfer SR2|SR1 status */
};

/************************************************************************************
 * Private Function Prototypes
 ************************************************************************************/

static inline uint32_t imxrt_lpi2c_getreg(FAR struct imxrt_lpi2c_priv_s *priv, uint16_t offset);
static inline void imxrt_lpi2c_putreg(FAR struct imxrt_lpi2c_priv_s *priv, uint16_t offset, uint32_t value);
static inline void imxrt_lpi2c_modifyreg(FAR struct imxrt_lpi2c_priv_s *priv, uint16_t offset, uint32_t clearbits, uint32_t setbits);
static inline void imxrt_lpi2c_sem_wait(FAR struct imxrt_lpi2c_priv_s *priv);

#ifdef CONFIG_IMXRT_I2C_DYNTIMEO
static useconds_t imxrt_lpi2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
#endif							/* CONFIG_IMXRT_I2C_DYNTIMEO */

static inline int imxrt_lpi2c_sem_waitdone(FAR struct imxrt_lpi2c_priv_s *priv);
static inline void imxrt_lpi2c_sem_waitstop(FAR struct imxrt_lpi2c_priv_s *priv);
static inline void imxrt_lpi2c_sem_post(FAR struct imxrt_lpi2c_priv_s *priv);
static inline void imxrt_lpi2c_sem_init(FAR struct imxrt_lpi2c_priv_s *priv);
static inline void imxrt_lpi2c_sem_destroy(FAR struct imxrt_lpi2c_priv_s *priv);

#ifdef CONFIG_I2C_TRACE
static void imxrt_lpi2c_tracereset(FAR struct imxrt_lpi2c_priv_s *priv);
static void imxrt_lpi2c_tracenew(FAR struct imxrt_lpi2c_priv_s *priv, uint32_t status);
static void imxrt_lpi2c_traceevent(FAR struct imxrt_lpi2c_priv_s *priv, enum imxrt_trace_e event, uint32_t parm);
static void imxrt_lpi2c_tracedump(FAR struct imxrt_lpi2c_priv_s *priv);
#endif							/* CONFIG_I2C_TRACE */

static void imxrt_lpi2c_setclock(FAR struct imxrt_lpi2c_priv_s *priv, uint32_t frequency);
static inline void imxrt_lpi2c_sendstart(FAR struct imxrt_lpi2c_priv_s *priv, uint8_t address);
static inline void imxrt_lpi2c_sendstop(FAR struct imxrt_lpi2c_priv_s *priv);
static inline uint32_t imxrt_lpi2c_getstatus(FAR struct imxrt_lpi2c_priv_s *priv);

static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv);

#ifndef CONFIG_I2C_POLLED
static int imxrt_lpi2c_isr(int irq, void *context, FAR void *arg);
#endif							/* !CONFIG_I2C_POLLED */

void imxrt_lpi2c_clock_enable(uint32_t base);
void imxrt_lpi2c_clock_disable(uint32_t base);
static int imxrt_lpi2c_init(FAR struct imxrt_lpi2c_priv_s *priv);
static int imxrt_lpi2c_deinit(FAR struct imxrt_lpi2c_priv_s *priv);
#ifdef CONFIG_I2C_TRANSFER
static int imxrt_lpi2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count);
#endif
#ifdef CONFIG_I2C_RESET
static int imxrt_lpi2c_reset(FAR struct i2c_master_s *dev);
#endif

static uint32_t imxrt_lpi2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency);
static int imxrt_lpi2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits);
static int imxrt_lpi2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen);
static int imxrt_lpi2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen);
#ifdef CONFIG_I2C_WRITEREAD
static int imxrt_lpi2c_writeread(FAR struct i2c_dev_s *dev, const uint8_t *wbuffer, int wbuflen, uint8_t *buffer, int buflen);
#endif

/************************************************************************************
 * Private Data
 ************************************************************************************/

/* Trace events strings */

#ifdef CONFIG_I2C_TRACE
static const char *g_trace_names[] = {
	"NONE           ",
	"SENDADDR       ",
	"SENDBYTE       ",
	"RCVBYTE        ",
	"NOSTART        ",
	"START/RESTART  ",
	"STOP           ",
	"ERROR          "
};
#endif

/* I2C interface */

static const struct i2c_ops_s imxrt_lpi2c_ops = {
	.setfrequency = imxrt_lpi2c_setfrequency,
	.setaddress = imxrt_lpi2c_setaddress,
	.write = imxrt_lpi2c_write,
	.read = imxrt_lpi2c_read,
#ifdef CONFIG_I2C_WRITEREAD
	.writeread = imxrt_lpi2c_writeread,
#endif
#ifdef CONFIG_I2C_TRANSFER
	.transfer = imxrt_lpi2c_transfer,
#endif
#ifdef CONFIG_I2C_SLAVE
	.setownaddress = imxrt_lpi2c_setownaddress,
	.registercallback = imxrt_lpi2c_registercallback
#endif
};

/* I2C device structures */

#ifdef CONFIG_IMXRT_LPI2C1
static const struct imxrt_lpi2c_config_s imxrt_lpi2c1_config = {
	.base = IMXRT_LPI2C1_BASE,
	.busy_idle = CONFIG_LPI2C1_BUSYIDLE,
	.filtscl = CONFIG_LPI2C1_FILTSCL,
	.filtsda = CONFIG_LPI2C1_FILTSDA,
	.scl_pin = GPIO_LPI2C1_SCL,
	.sda_pin = GPIO_LPI2C1_SDA,
#ifndef CONFIG_I2C_SLAVE
	.mode = LPI2C_MASTER,
#else
	.mode = LPI2C_SLAVE,
#endif
#ifndef CONFIG_I2C_POLLED
	.irq = IMXRT_IRQ_LPI2C1,
#endif
};

static struct imxrt_lpi2c_priv_s imxrt_lpi2c1_priv = {
	.ops = &imxrt_lpi2c_ops,
	.config = &imxrt_lpi2c1_config,
	.refs = 0,
	.intstate = INTSTATE_IDLE,
	.msgc = 0,
	.msgv = NULL,
	.ptr = NULL,
	.dcnt = 0,
	.flags = 0,
	.status = 0
};
#endif

#ifdef CONFIG_IMXRT_LPI2C2
static const struct imxrt_lpi2c_config_s imxrt_lpi2c2_config = {
	.base = IMXRT_LPI2C2_BASE,
	.busy_idle = CONFIG_LPI2C2_BUSYIDLE,
	.filtscl = CONFIG_LPI2C2_FILTSCL,
	.filtsda = CONFIG_LPI2C2_FILTSDA,
	.scl_pin = GPIO_LPI2C2_SCL,
	.sda_pin = GPIO_LPI2C2_SDA,
#ifndef CONFIG_I2C_SLAVE
	.mode = LPI2C_MASTER,
#else
	.mode = LPI2C_SLAVE,
#endif
#ifndef CONFIG_I2C_POLLED
	.irq = IMXRT_IRQ_LPI2C2,
#endif
};

static struct imxrt_lpi2c_priv_s imxrt_lpi2c2_priv = {
	.ops = &imxrt_lpi2c_ops,
	.config = &imxrt_lpi2c2_config,
	.refs = 0,
	.intstate = INTSTATE_IDLE,
	.msgc = 0,
	.msgv = NULL,
	.ptr = NULL,
	.dcnt = 0,
	.flags = 0,
	.status = 0
};
#endif

#ifdef CONFIG_IMXRT_LPI2C3
static const struct imxrt_lpi2c_config_s imxrt_lpi2c3_config = {
	.base = IMXRT_LPI2C3_BASE,
	.busy_idle = CONFIG_LPI2C3_BUSYIDLE,
	.filtscl = CONFIG_LPI2C3_FILTSCL,
	.filtsda = CONFIG_LPI2C3_FILTSDA,
	.scl_pin = GPIO_LPI2C3_SCL,
	.sda_pin = GPIO_LPI2C3_SDA,
#ifndef CONFIG_I2C_SLAVE
	.mode = LPI2C_MASTER,
#else
	.mode = LPI2C_SLAVE,
#endif
#ifndef CONFIG_I2C_POLLED
	.irq = IMXRT_IRQ_LPI2C3,
#endif
};

static struct imxrt_lpi2c_priv_s imxrt_lpi2c3_priv = {
	.ops = &imxrt_lpi2c_ops,
	.config = &imxrt_lpi2c3_config,
	.refs = 0,
	.intstate = INTSTATE_IDLE,
	.msgc = 0,
	.msgv = NULL,
	.ptr = NULL,
	.dcnt = 0,
	.flags = 0,
	.status = 0
};
#endif

#ifdef CONFIG_IMXRT_LPI2C4
static const struct imxrt_lpi2c_config_s imxrt_lpi2c4_config = {
	.base = IMXRT_LPI2C4_BASE,
	.busy_idle = CONFIG_LPI2C4_BUSYIDLE,
	.filtscl = CONFIG_LPI2C4_FILTSCL,
	.filtsda = CONFIG_LPI2C4_FILTSDA,
	.scl_pin = GPIO_LPI2C4_SCL,
	.sda_pin = GPIO_LPI2C4_SDA,
#ifndef CONFIG_I2C_SLAVE
	.mode = LPI2C_MASTER,
#else
	.mode = LPI2C_SLAVE,
#endif
#ifndef CONFIG_I2C_POLLED
	.irq = IMXRT_IRQ_LPI2C4,
#endif
};

static struct imxrt_lpi2c_priv_s imxrt_lpi2c4_priv = {
	.ops = &imxrt_lpi2c_ops,
	.config = &imxrt_lpi2c4_config,
	.refs = 0,
	.intstate = INTSTATE_IDLE,
	.msgc = 0,
	.msgv = NULL,
	.ptr = NULL,
	.dcnt = 0,
	.flags = 0,
	.status = 0
};
#endif

/************************************************************************************
 * Private Functions
 ************************************************************************************/

/************************************************************************************
 * Name: imxrt_lpi2c_getreg
 *
 * Description:
 *   Get a 32-bit register value by offset
 *
 ************************************************************************************/

static inline uint32_t imxrt_lpi2c_getreg(FAR struct imxrt_lpi2c_priv_s *priv, uint16_t offset)
{
	return getreg32(priv->config->base + offset);
}

/************************************************************************************
 * Name: imxrt_lpi2c_putreg
 *
 * Description:
 *  Put a 32-bit register value by offset
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_putreg(FAR struct imxrt_lpi2c_priv_s *priv, uint16_t offset, uint32_t value)
{
	putreg32(value, priv->config->base + offset);
}

/************************************************************************************
 * Name: imxrt_lpi2c_modifyreg
 *
 * Description:
 *   Modify a 32-bit register value by offset
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_modifyreg(FAR struct imxrt_lpi2c_priv_s *priv, uint16_t offset, uint32_t clearbits, uint32_t setbits)
{
	modifyreg32(priv->config->base + offset, clearbits, setbits);
}

/************************************************************************************
 * Name: imxrt_lpi2c_sem_wait
 *
 * Description:
 *   Take the exclusive access, waiting as necessary
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_sem_wait(FAR struct imxrt_lpi2c_priv_s *priv)
{
	int ret;

	do {
		/* Take the semaphore (perhaps waiting) */

		ret = sem_wait(&priv->sem_excl);

		/* The only case that an error should occur here is if the wait was
		 * awakened by a signal.
		 */

		DEBUGASSERT(ret == OK || ret == -EINTR);
	} while (ret == -EINTR);
}

/************************************************************************************
 * Name: imxrt_lpi2c_tousecs
 *
 * Description:
 *   Return a micro-second delay based on the number of bytes left to be processed.
 *
 ************************************************************************************/

#ifdef CONFIG_IMXRT_I2C_DYNTIMEO
static useconds_t imxrt_lpi2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
{
	size_t bytecount = 0;
	int i;

	/* Count the number of bytes left to process */

	for (i = 0; i < msgc; i++) {
		bytecount += msgs[i].length;
	}

	/* Then return a number of microseconds based on a user provided scaling
	 * factor.
	 */

	return (useconds_t)(CONFIG_IMXRT_I2C_DYNTIMEO_USECPERBYTE * bytecount);
}
#endif

/************************************************************************************
 * Name: imxrt_lpi2c_sem_waitdone
 *
 * Description:
 *   Wait for a transfer to complete
 *
 ************************************************************************************/

#ifndef CONFIG_I2C_POLLED
static inline int imxrt_lpi2c_sem_waitdone(FAR struct imxrt_lpi2c_priv_s *priv)
{
	struct timespec abstime;
	irqstate_t flags;
	uint32_t regval;
	int ret;

	flags = irqsave();

	/* Enable Interrupts when master mode */

	if (priv->config->mode == LPI2C_MASTER) {
		if ((priv->flags & I2C_M_READ) != 0) {
			regval = LPI2C_MIER_TDIE(1U) | LPI2C_MIER_RDIE(1U) | LPI2C_MIER_NDIE(1U) | LPI2C_MIER_ALIE(1U) | LPI2C_MIER_SDIE(1U);
			imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, regval);
		} else {
			regval = LPI2C_MIER_TDIE(1U) | LPI2C_MIER_NDIE(1U) | LPI2C_MIER_ALIE(1U) | LPI2C_MIER_SDIE(1U);
			imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, regval);
		}

	}

	/* Enable Interrupts when slave mode */

	else {
#warning Missing logic for I2C Slave mode
	}

	/* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
	 * are currently disabled but will be temporarily re-enabled below when
	 * sem_timedwait() sleeps.
	 */

	priv->intstate = INTSTATE_WAITING;
	do {
		/* Get the current time */

		(void)clock_gettime(CLOCK_REALTIME, &abstime);

		/* Calculate a time in the future */

#if CONFIG_IMXRT_I2CTIMEOSEC > 0
		abstime.tv_sec += CONFIG_IMXRT_I2CTIMEOSEC;
#endif

		/* Add a value proportional to the number of bytes in the transfer */

#ifdef CONFIG_IMXRT_I2C_DYNTIMEO
		abstime.tv_nsec += 1000 * imxrt_lpi2c_tousecs(priv->msgc, priv->msgv);
		if (abstime.tv_nsec >= 1000 * 1000 * 1000) {
			abstime.tv_sec++;
			abstime.tv_nsec -= 1000 * 1000 * 1000;
		}
#elif CONFIG_IMXRT_I2CTIMEOMS > 0
		abstime.tv_nsec += CONFIG_IMXRT_I2CTIMEOMS * 1000 * 1000;
		if (abstime.tv_nsec >= 1000 * 1000 * 1000) {
			abstime.tv_sec++;
			abstime.tv_nsec -= 1000 * 1000 * 1000;
		}
#endif

		/* Wait until either the transfer is complete or the timeout expires */

		ret = sem_timedwait(&priv->sem_isr, &abstime);
		if (ret < 0 && ret != -EINTR) {
			/* Break out of the loop on irrecoverable errors.  This would
			 * include timeouts and mystery errors reported by sem_timedwait.
			 * NOTE that we try again if we are awakened by a signal (EINTR).
			 */

			break;
		}
	}

	/* Loop until the interrupt level transfer is complete. */

	while (priv->intstate != INTSTATE_DONE);

	/* Set the interrupt state back to IDLE */

	priv->intstate = INTSTATE_IDLE;

	/* Disable I2C interrupts */

	/* Enable Interrupts when master mode */

	if (priv->config->mode == LPI2C_MASTER) {
		imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MIER_OFFSET, 0);
	} else {

		/* Enable Interrupts when slave mode */

		imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_SIER_OFFSET, 0);
	}

	irqrestore(flags);
	return ret;
}
#else
static inline int imxrt_lpi2c_sem_waitdone(FAR struct imxrt_lpi2c_priv_s *priv)
{
	clock_t timeout;
	clock_t start;
	clock_t elapsed;
	int ret;

	/* Get the timeout value */

#ifdef CONFIG_IMXRT_I2C_DYNTIMEO
	timeout = USEC2TICK(imxrt_lpi2c_tousecs(priv->msgc, priv->msgv));
#else
	timeout = CONFIG_IMXRT_I2CTIMEOTICKS;
#endif

	/* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
	 * are currently disabled but will be temporarily re-enabled below when
	 * sem_timedwait() sleeps.
	 */

	priv->intstate = INTSTATE_WAITING;
	start = clock_systimer();

	do {
		/* Calculate the elapsed time */

		elapsed = clock_systimer() - start;

		/* Poll by simply calling the timer interrupt handler until it
		 * reports that it is done.
		 */

		imxrt_lpi2c_isr_process(priv);
	}

	/* Loop until the transfer is complete. */

	while (priv->intstate != INTSTATE_DONE && elapsed < timeout);

	i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n", priv->intstate, (long)elapsed, (long)timeout, priv->status);

	/* Set the interrupt state back to IDLE */

	ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT;
	priv->intstate = INTSTATE_IDLE;
	return ret;
}
#endif

/************************************************************************************
 * Name: imxrt_lpi2c_sem_waitstop
 *
 * Description:
 *   Wait for a STOP to complete
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_sem_waitstop(FAR struct imxrt_lpi2c_priv_s *priv)
{
	clock_t start;
	clock_t elapsed;
	clock_t timeout;
	uint32_t regval;

	/* Select a timeout */

#ifdef CONFIG_IMXRT_I2C_DYNTIMEO
	timeout = USEC2TICK(CONFIG_IMXRT_I2C_DYNTIMEO_STARTSTOP);
#else
	timeout = CONFIG_IMXRT_I2CTIMEOTICKS;
#endif

	/* Wait as stop might still be in progress; but stop might also
	 * be set because of a timeout error: "The [STOP] bit is set and
	 * cleared by software, cleared by hardware when a Stop condition is
	 * detected, set by hardware when a timeout error is detected."
	 */

	start = clock_systimer();
	do {
		/* Calculate the elapsed time */

		elapsed = clock_systimer() - start;

		/* Check for STOP condition */

		if (priv->config->mode == LPI2C_MASTER) {
			regval = imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MSR_OFFSET);
			if ((regval & LPI2C_MSR_SDF(1U)) == LPI2C_MSR_SDF(1U)) {
				return;
			}
		}

		/* Enable Interrupts when slave mode */

		else {
			regval = imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_SSR_OFFSET);
			if ((regval & LPI2C_SSR_SDF(1U)) == LPI2C_SSR_SDF(1U)) {
				return;
			}
		}

		/* Check for NACK error */

		if (priv->config->mode == LPI2C_MASTER) {
			regval = imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MSR_OFFSET);
			if ((regval & LPI2C_MSR_NDF(1U)) == LPI2C_MSR_NDF(1U)) {
				return;
			}
		}

		/* Enable Interrupts when slave mode */

		else {
#warning Missing logic for I2C Slave
		}
	}

	/* Loop until the stop is complete or a timeout occurs. */

	while (elapsed < timeout);

	/* If we get here then a timeout occurred with the STOP condition
	 * still pending.
	 */

	i2cinfo("Timeout with Status Register: %x\n", regval);
}

/************************************************************************************
 * Name: imxrt_lpi2c_sem_post
 *
 * Description:
 *   Release the mutual exclusion semaphore
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_sem_post(struct imxrt_lpi2c_priv_s *priv)
{
	sem_post(&priv->sem_excl);
}

/************************************************************************************
 * Name: imxrt_lpi2c_sem_init
 *
 * Description:
 *   Initialize semaphores
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_sem_init(FAR struct imxrt_lpi2c_priv_s *priv)
{
	sem_init(&priv->sem_excl, 0, 1);

#ifndef CONFIG_I2C_POLLED
	/* This semaphore is used for signaling and, hence, should not have
	 * priority inheritance enabled.
	 */

	sem_init(&priv->sem_isr, 0, 0);
	sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

/************************************************************************************
 * Name: imxrt_lpi2c_sem_destroy
 *
 * Description:
 *   Destroy semaphores.
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_sem_destroy(FAR struct imxrt_lpi2c_priv_s *priv)
{
	sem_destroy(&priv->sem_excl);
#ifndef CONFIG_I2C_POLLED
	sem_destroy(&priv->sem_isr);
#endif
}

/************************************************************************************
 * Name: imxrt_lpi2c_trace*
 *
 * Description:
 *   I2C trace instrumentation
 *
 ************************************************************************************/

#ifdef CONFIG_I2C_TRACE
static void imxrt_lpi2c_traceclear(FAR struct imxrt_lpi2c_priv_s *priv)
{
	struct imxrt_trace_s *trace = &priv->trace[priv->tndx];

	trace->status = 0;			/* I2C 32-bit SR2|SR1 status */
	trace->count = 0;			/* Interrupt count when status change */
	trace->event = I2CEVENT_NONE;	/* Last event that occurred with this status */
	trace->parm = 0;			/* Parameter associated with the event */
	trace->time = 0;			/* Time of first status or event */
}

static void imxrt_lpi2c_tracereset(FAR struct imxrt_lpi2c_priv_s *priv)
{
	/* Reset the trace info for a new data collection */

	priv->tndx = 0;
	priv->start_time = clock_systimer();
	imxrt_lpi2c_traceclear(priv);
}

static void imxrt_lpi2c_tracenew(FAR struct imxrt_lpi2c_priv_s *priv, uint32_t status)
{
	struct imxrt_trace_s *trace = &priv->trace[priv->tndx];

	/* Is the current entry uninitialized?  Has the status changed? */

	if (trace->count == 0 || status != trace->status) {
		/* Yes.. Was it the status changed?  */

		if (trace->count != 0) {
			/* Yes.. bump up the trace index (unless we are out of trace entries) */

			if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) {
				i2cerr("ERROR: Trace table overflow\n");
				return;
			}

			priv->tndx++;
			trace = &priv->trace[priv->tndx];
		}

		/* Initialize the new trace entry */

		imxrt_lpi2c_traceclear(priv);
		trace->status = status;
		trace->count = 1;
		trace->time = clock_systimer();
	} else {
		/* Just increment the count of times that we have seen this status */

		trace->count++;
	}
}

static void imxrt_lpi2c_traceevent(FAR struct imxrt_lpi2c_priv_s *priv, enum imxrt_trace_e event, uint32_t parm)
{
	struct imxrt_trace_s *trace;

	if (event != I2CEVENT_NONE) {
		trace = &priv->trace[priv->tndx];

		/* Initialize the new trace entry */

		trace->event = event;
		trace->parm = parm;

		/* Bump up the trace index (unless we are out of trace entries) */

		if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) {
			i2cerr("ERROR: Trace table overflow\n");
			return;
		}

		priv->tndx++;
		imxrt_lpi2c_traceclear(priv);
	}
}

static void imxrt_lpi2c_tracedump(FAR struct imxrt_lpi2c_priv_s *priv)
{
	struct imxrt_trace_s *trace;
	int i;

	syslog(LOG_DEBUG, "Elapsed time: %ld\n", (long)(clock_systimer() - priv->start_time));

	for (i = 0; i <= priv->tndx; i++) {
		trace = &priv->trace[i];
		syslog(LOG_DEBUG, "%2d. STATUS: %08x COUNT: %3d EVENT: %s(%2d) PARM: %08x TIME: %d\n",
		       i + 1, trace->status, trace->count, g_trace_names[trace->event], trace->event,
		       trace->parm, trace->time - priv->start_time);
	}
}
#endif							/* CONFIG_I2C_TRACE */

/************************************************************************************
 * Name: imxrt_lpi2c_setclock
 *
 * Description:
 *   Set the I2C clock
 *
 ************************************************************************************/

static void imxrt_lpi2c_setclock(FAR struct imxrt_lpi2c_priv_s *priv, uint32_t frequency)
{
	uint32_t src_freq = 0;
	uint32_t pll3_div = 0;
	uint32_t lpi2c_clk_div;
	uint32_t regval;
	uint32_t men;
	uint32_t prescale = 0;
	uint32_t best_prescale = 0;
	uint32_t best_clk_hi = 0;
	uint32_t abs_error = 0;
	uint32_t best_error = 0xffffffff;
	uint32_t clk_hi_cycle;
	uint32_t computed_rate;
	uint32_t count;

	/* Has the I2C bus frequency changed? */

	if (priv->config->mode == LPI2C_MASTER) {
		if (frequency != priv->frequency) {
			/* Disable the selected LPI2C peripheral to configure the new
			 * clock if it is enabled.
			 */

			men = imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MCR_OFFSET) & LPI2C_MCR_MEN(1U);
			if (men) {
				imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCR_OFFSET, LPI2C_MCR_MEN(1U), 0);
			}

			/* Get the LPI2C clock source frequency */

			if ((getreg32(IMXRT_CCM_CSCDR2) & CCM_CSCDR2_LPI2C_CLK_SEL(1U)) == CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK) {
				src_freq = BOARD_XTAL_FREQUENCY;
			} else {
				if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0) {
					pll3_div = 22;
				} else {
					pll3_div = 20;
				}

				lpi2c_clk_div = (getreg32(IMXRT_CCM_CSCDR2) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) >> CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT;
				lpi2c_clk_div = lpi2c_clk_div + 1;
				src_freq = (BOARD_XTAL_FREQUENCY * pll3_div) / (8 * lpi2c_clk_div);
			}

			/* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) / (CLKLO + 1 + CLKHI + 1 +
			 * ROUNDDOWN((2 + FILTSCL) / 2^prescale)
			 *
			 * Assume  CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2
			 */

			for (prescale = 1; (prescale <= 128) && (best_error != 0); prescale *= 2) {
				for (clk_hi_cycle = 1; clk_hi_cycle < 32; clk_hi_cycle++) {
					if (clk_hi_cycle == 1) {
						computed_rate = (src_freq / prescale) / (6 + (2 / prescale));
					} else {
						computed_rate = (src_freq / prescale) / ((3 * clk_hi_cycle + 2) + (2 / prescale));
					}

					if (frequency > computed_rate) {
						abs_error = frequency - computed_rate;
					} else {
						abs_error = computed_rate - frequency;
					}

					if (abs_error < best_error) {
						best_prescale = prescale;
						best_clk_hi = clk_hi_cycle;
						best_error = abs_error;

						if (abs_error == 0) {
							break;
						}
					}
				}
			}

			regval = LPI2C_MCCR0_CLKHI(best_clk_hi);

			if (best_clk_hi < 2) {
				regval |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
			} else {
				regval |= LPI2C_MCCR0_CLKLO(2 * best_clk_hi) | LPI2C_MCCR0_SETHOLD(best_clk_hi) | LPI2C_MCCR0_DATAVD(best_clk_hi / 2);
			}

			imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCCR0_OFFSET, regval);

			for (count = 0; count < 8; count++) {
				if (best_prescale == (1 << count)) {
					best_prescale = count;
					break;
				}
			}

			imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR1_OFFSET, 0, LPI2C_MCFGR1_PRESCALE(best_prescale));

			/* Re-enable LPI2C if it was enabled previously */

			if (men) {
				imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCR_OFFSET, 0, LPI2C_MCR_MEN(1U));
			}

			/* Save the new LPI2C frequency */

			priv->frequency = frequency;
		}
	}
}

/************************************************************************************
 * Name: imxrt_lpi2c_sendstart
 *
 * Description:
 *   Send the START conditions/force Master mode
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_sendstart(FAR struct imxrt_lpi2c_priv_s *priv, uint8_t address)
{
	uint32_t txcount = 0;
	uint32_t status = 0;
	uint8_t addr;

	/* Generate START condition and send the address */
	/* Turn off auto_stop option */

	imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR1_OFFSET, LPI2C_MCFGR1_IGNACK(1U), 0);

	do {
		txcount = (imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MFSR_OFFSET) & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT;
		txcount = 4 - txcount;

		status = imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MSR_OFFSET);

		if (status & LPI2C_MSR_ERROR_MASK) {
			imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET, status & LPI2C_MSR_ERROR_MASK);
		}
	} while (txcount == 0);

	if ((priv->flags & I2C_M_READ) != 0) {
		addr = address | 0x01;
	} else {
		addr = address;
	}

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MTDR_OFFSET, (LPI2C_MTDR_CMD_START | LPI2C_MTDR_DATA(addr)));
}

/************************************************************************************
 * Name: imxrt_lpi2c_sendstop
 *
 * Description:
 *   Send the STOP conditions
 *
 ************************************************************************************/

static inline void imxrt_lpi2c_sendstop(FAR struct imxrt_lpi2c_priv_s *priv)
{
	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MTDR_OFFSET, LPI2C_MTDR_CMD_STOP);
}

/************************************************************************************
 * Name: imxrt_lpi2c_getstatus
 *
 * Description:
 *   Get 32-bit status
 *
 ************************************************************************************/

static inline uint32_t imxrt_lpi2c_getstatus(FAR struct imxrt_lpi2c_priv_s *priv)
{
	return imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MSR_OFFSET);
}

/************************************************************************************
 * Name: imxrt_lpi2c_isr_process
 *
 * Description:
 *  Common Interrupt Service Routine
 *
 ************************************************************************************/

static int imxrt_lpi2c_isr_process(struct imxrt_lpi2c_priv_s *priv)
{
	uint32_t status = imxrt_lpi2c_getstatus(priv);

	/* Check for new trace setup */

	imxrt_lpi2c_tracenew(priv, status);

	/* Continue with either sending or reading data */

	/* Check if there is more butes to send */

	if (((priv->flags & I2C_M_READ) == 0) && (status & LPI2C_MSR_TDF(1U)) != 0) {
		if (priv->dcnt > 0) {
			imxrt_lpi2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt);
			imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MTDR_OFFSET, LPI2C_MTDR_CMD_TXD | LPI2C_MTDR_DATA(*priv->ptr++));
			priv->dcnt--;

			if ((priv->msgc <= 0) && (priv->dcnt == 0)) {
				imxrt_lpi2c_sendstop(priv);
			}
		}
	}

	/* Check if there is more bytes to read */

	else if (((priv->flags & I2C_M_READ) != 0) && (status & LPI2C_MSR_RDF(1U)) != 0) {
		/* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */

		if (priv->dcnt > 0) {
			imxrt_lpi2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);

			/* No interrupts or contex switches should occur in the following
			 * seuence. Otherwise, additional bytes may be sent by the device.
			 */

#ifdef CONFIG_I2C_POLLED
			irqstate_t flags = irqsave();
#endif

			/* Receive a byte */

			*priv->ptr++ = imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MRDR_OFFSET) & LPI2C_MRDR_DATA_MASK;
			priv->dcnt--;

#ifdef CONFIG_I2C_POLLED
			irqrestore(flags);
#endif
			if ((priv->msgc <= 0) && (priv->dcnt == 0)) {
				imxrt_lpi2c_sendstop(priv);
			}
		} else {
			imxrt_lpi2c_getreg(priv, IMXRT_LPI2C_MRDR_OFFSET);
		}
	}

	if (priv->dcnt <= 0) {
		if (priv->msgc > 0 && priv->msgv != NULL) {
			priv->ptr = priv->msgv->buffer;
			priv->dcnt = priv->msgv->length;
			priv->flags = priv->msgv->flags;

			if ((priv->msgv->flags & I2C_M_NOSTART) == 0) {
				imxrt_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, priv->msgc);
				imxrt_lpi2c_sendstart(priv, priv->msgv->addr);
			} else {
				imxrt_lpi2c_traceevent(priv, I2CEVENT_NOSTART, priv->msgc);
			}

			priv->msgv++;
			priv->msgc--;

			if ((priv->flags & I2C_M_READ) != 0) {
#ifndef CONFIG_I2C_POLLED
				/* Stop TX interrupt */

				imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MIER_OFFSET, LPI2C_MIER_TDIE(1U), LPI2C_MIER_RDIE(1U));
#endif
				/* Set LPI2C in read mode */
				imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MTDR_OFFSET, LPI2C_MTDR_CMD_RXD | LPI2C_MTDR_DATA((priv->dcnt - 1)));
			} else {
				/* Send the first byte from tx buffer */

				imxrt_lpi2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt);
				imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MTDR_OFFSET, LPI2C_MTDR_CMD_TXD | LPI2C_MTDR_DATA(*priv->ptr++));
				priv->dcnt--;
				if ((priv->msgc <= 0) && (priv->dcnt == 0)) {
					imxrt_lpi2c_sendstop(priv);
				}
			}
		} else if (priv->msgv && ((status & LPI2C_MSR_SDF(1U)) != 0)) {
			imxrt_lpi2c_traceevent(priv, I2CEVENT_STOP, 0);
			imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET, LPI2C_MSR_SDF(1U));

			/* Check is there thread waiting for this event (there should be) */

#ifndef CONFIG_I2C_POLLED
			if (priv->intstate == INTSTATE_WAITING) {
				/* inform the thread that transfer is complete
				 * and wake it up
				 */

				sem_post(&priv->sem_isr);
				priv->intstate = INTSTATE_DONE;
			}
#else
			priv->intstate = INTSTATE_DONE;
#endif
			/* Mark that this transaction stopped */

			priv->msgv = NULL;
		}
#ifndef CONFIG_I2C_POLLED
		else {
			imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MIER_OFFSET, LPI2C_MIER_TDIE(1U) | LPI2C_MIER_RDIE(1U), 0);
		}
#endif
	}

	/* Check for errors */

	if ((status & LPI2C_MSR_EPF(1U)) != 0) {
		imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET, LPI2C_MSR_EPF(1U));
	}

	if ((status & (LPI2C_MSR_NDF(1U) | LPI2C_MSR_ALF(1U) | LPI2C_MSR_FEF(1U))) != 0) {
		imxrt_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0);

		/* Clear the error */

		imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET, (status & (LPI2C_MSR_NDF(1U) | LPI2C_MSR_ALF(1U) | LPI2C_MSR_FEF(1U))));

#ifndef CONFIG_I2C_POLLED
		if (priv->intstate == INTSTATE_WAITING) {
			/* inform the thread that transfer is complete
			 * and wake it up
			 */

			sem_post(&priv->sem_isr);
			priv->intstate = INTSTATE_DONE;
		}
#else
		priv->intstate = INTSTATE_DONE;
#endif
	}

	priv->status = status;
	return OK;
}

/************************************************************************************
 * Name: imxrt_lpi2c_isr
 *
 * Description:
 *   Common I2C interrupt service routine
 *
 ************************************************************************************/

#ifndef CONFIG_I2C_POLLED
static int imxrt_lpi2c_isr(int irq, void *context, FAR void *arg)
{
	struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)arg;

	DEBUGASSERT(priv != NULL);
	return imxrt_lpi2c_isr_process(priv);
}
#endif

/************************************************************************************
 * Name: imxrt_lpi2c_clock_enable
 *
 * Description:
 *   Ungate LPI2C clock
 *
 ************************************************************************************/

void imxrt_lpi2c_clock_enable(uint32_t base)
{
	if (base == IMXRT_LPI2C1_BASE) {
		imxrt_clockall_lpi2c1();
	} else if (base == IMXRT_LPI2C2_BASE) {
		imxrt_clockall_lpi2c2();
	} else if (base == IMXRT_LPI2C3_BASE) {
		imxrt_clockall_lpi2c3();
	} else if (base == IMXRT_LPI2C4_BASE) {
		imxrt_clockall_lpi2c4_serial();
	}
}

/************************************************************************************
 * Name: imxrt_lpi2c_clock_disable
 *
 * Description:
 *   Gate LPI2C clock
 *
 ************************************************************************************/

void imxrt_lpi2c_clock_disable(uint32_t base)
{
	if (base == IMXRT_LPI2C1_BASE) {
		imxrt_clockoff_lpi2c1();
	} else if (base == IMXRT_LPI2C2_BASE) {
		imxrt_clockoff_lpi2c2();
	} else if (base == IMXRT_LPI2C3_BASE) {
		imxrt_clockoff_lpi2c3();
	} else if (base == IMXRT_LPI2C4_BASE) {
		imxrt_clockoff_lpi2c4_serial();
	}
}

/************************************************************************************
 * Name: imxrt_lpi2c_init
 *
 * Description:
 *   Setup the I2C hardware, ready for operation with defaults
 *
 ************************************************************************************/

static int imxrt_lpi2c_init(FAR struct imxrt_lpi2c_priv_s *priv)
{
	/* Power-up and configure GPIOs */

	/* Configure pins */

	(void)imxrt_config_gpio(priv->config->scl_pin);
	(void)imxrt_config_gpio(priv->config->sda_pin);

	/* Enable power and reset the peripheral */

	imxrt_lpi2c_clock_enable(priv->config->base);

	/* Reset LPI2C before configuring it */

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCR_OFFSET, LPI2C_MCR_RST(1U));
	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCR_OFFSET, 0);

	/* Disable doze mode (Set DOZEN bit in 1 to disable) */

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCR_OFFSET, LPI2C_MCR_DOZEN(1U));

	/* Disable host request */

	imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR0_OFFSET, LPI2C_MCFG0_HREN | LPI2C_MCFG0_HRSEL, LPI2C_MCFG0_HRPOL);

	/* Pin config and ignore NACK disable */

	imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCFGR1_OFFSET, LPI2C_MCFGR1_IGNACK(1U) | LPI2C_MCFGR1_PINCFG_MASK, 0);

	/* Set tx and rx watermarks */

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MFCR_OFFSET, LPI2C_MFCR_TXWATER(0) | LPI2C_MFCR_RXWATER(0));

	/* Force a frequency update */

	priv->frequency = 0;
	imxrt_lpi2c_setclock(priv, 100000);

	/* Set scl, sda glitch filters and busy idle */

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCFGR2_OFFSET, LPI2C_MCFG2_BUSIDLE(priv->config->busy_idle) |
			   LPI2C_MCFG2_FILTSCL_CYCLES(priv->config->filtscl) | LPI2C_MCFG2_FILTSDA_CYCLES(priv->config->filtsda));

	/* Set pin low cycles to 0 (disable) */

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCFGR3_OFFSET, LPI2C_MCFG3_PINLOW_CYCLES(0));

	/* Attach ISRs */

#ifndef CONFIG_I2C_POLLED
	irq_attach(priv->config->irq, imxrt_lpi2c_isr, priv);
	up_enable_irq(priv->config->irq);
#endif

	/* Enable I2C */

	imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCR_OFFSET, 0, LPI2C_MCR_MEN(1U));
	return OK;
}

/************************************************************************************
 * Name: imxrt_lpi2c_deinit
 *
 * Description:
 *   Shutdown the I2C hardware
 *
 ************************************************************************************/

static int imxrt_lpi2c_deinit(FAR struct imxrt_lpi2c_priv_s *priv)
{
	/* Disable I2C */

	imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MCR_OFFSET, LPI2C_MCR_MEN(1U), 0);

	/* Reset LPI2C */

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCR_OFFSET, LPI2C_MCR_RST(1U));
	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MCR_OFFSET, 0);

	/* Disable and detach interrupts */

#ifndef CONFIG_I2C_POLLED
	up_disable_irq(priv->config->irq);
	irq_detach(priv->config->irq);
#endif

	/* Disable clocking */

	imxrt_lpi2c_clock_disable(priv->config->base);

	return OK;
}

/************************************************************************************
 * Device Driver Operations
 ************************************************************************************/
/************************************************************************************
 * Name: imxrt_lpi2c_setfrequency
 *
 * Description:
 *   Set the I2C frequency
 *
 ************************************************************************************/
static uint32_t imxrt_lpi2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)dev;

	imxrt_lpi2c_sem_wait(priv);

	((struct imxrt_lpi2c_priv_s *)dev)->frequency = frequency;

	imxrt_lpi2c_sem_post(priv);
	return ((struct imxrt_lpi2c_priv_s *)dev)->frequency;
}

/************************************************************************************
 * Name: imxrt_lpi2c_setaddress
 *
 * Description:
 *   Set the I2C slave address
 *
 ************************************************************************************/

static int imxrt_lpi2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)dev;

	imxrt_lpi2c_sem_wait(priv);

	((struct imxrt_lpi2c_priv_s *)dev)->address = addr;
	((struct imxrt_lpi2c_priv_s *)dev)->flags = (nbits == 10) ? I2C_M_TEN : 0;

	imxrt_lpi2c_sem_post(priv);
	return OK;
}

/************************************************************************************
 * Name: imxrt_lpi2c_write
 *
 * Description:
 *   Write I2C data
 *
 ************************************************************************************/

static int imxrt_lpi2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)dev;

	imxrt_lpi2c_sem_wait(priv);	/* ensure that address or flags don't change meanwhile */

	priv->msgv[0].addr = priv->address;
	priv->msgv[0].flags = priv->flags;
	priv->msgv[0].buffer = (uint8_t *)buffer;
	priv->msgv[0].length = buflen;

	priv->msgc = 1;

	imxrt_lpi2c_sem_waitdone(priv);

	imxrt_lpi2c_sem_post(priv);

	return 0;
}

/************************************************************************************
 * Name: imxrt_lpi2c_read
 *
 * Description:
 *   Read I2C data
 *
 ************************************************************************************/

static int imxrt_lpi2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)dev;

	imxrt_lpi2c_sem_wait(priv);	/* ensure that address or flags don't change meanwhile */

	priv->msgv[0].addr = priv->address;
	priv->msgv[0].flags = priv->flags | I2C_M_READ;
	priv->msgv[0].buffer = buffer;
	priv->msgv[0].length = buflen;

	priv->msgc = 1;

	imxrt_lpi2c_sem_waitdone(priv);

	imxrt_lpi2c_sem_post(priv);

	return 0;
}

/************************************************************************************
 * Name: imxrt_lpi2c_writeread
 *
 * Description:
 *  Read then write I2C data
 *
 ************************************************************************************/

#ifdef CONFIG_I2C_WRITEREAD
static int imxrt_lpi2c_writeread(FAR struct i2c_dev_s *dev, const uint8_t *wbuffer, int wbuflen, uint8_t *buffer, int buflen)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)dev;

	imxrt_lpi2c_sem_wait(priv);	/* Ensure that address or flags don't change meanwhile */

	priv->msgv[0].addr = priv->address;
	priv->msgv[0].flags = priv->flags;
	priv->msgv[0].buffer = (uint8_t *)wbuffer;
	priv->msgv[0].length = wbuflen;

	priv->msgv[1].addr = priv->address;
	priv->msgv[1].flags = priv->flags | ((buflen > 0) ? I2C_M_READ : I2C_M_NORESTART);
	priv->msgv[1].buffer = buffer;
	priv->msgv[1].length = (buflen > 0) ? buflen : -buflen;

	pirv->msgc = 2;

	imxrt_lpi2c_sem_waitdone(priv);

	mxrt_lpi2c_sem_post(priv);

	return 0;
}
#endif

#ifdef CONFIG_I2C_TRANSFER
/************************************************************************************
 * Name: imxrt_lpi2c_transfer
 *
 * Description:
 *   Generic I2C transfer function
 *
 ************************************************************************************/

static int imxrt_lpi2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)dev;
	uint32_t status = 0;

	int ret = 0;

	DEBUGASSERT(count > 0);

	/* Ensure that address or flags don't change meanwhile */

	imxrt_lpi2c_sem_wait(priv);

	/* Clear any pending error interrupts */

	imxrt_lpi2c_putreg(priv, IMXRT_LPI2C_MSR_OFFSET, 0xffffffff);

	/* Old transfers are done */

	/* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't
	 * overwrite stale data.
	 */

	priv->dcnt = 0;
	priv->ptr = NULL;

	priv->msgv = msgs;
	priv->msgc = count;
	priv->flags = msgs->flags;

	i2cinfo("Flags %d, len %d \n", msgs->flags, msgs->length);

	/* Reset I2C trace logic */

	imxrt_lpi2c_tracereset(priv);

	/* Set I2C clock frequency */

	imxrt_lpi2c_setclock(priv, priv->frequency);

	priv->status = 0;

	/* Wait for an ISR, if there was a timeout, fetch latest status to get
	 * the BUSY flag.
	 */

	if (imxrt_lpi2c_sem_waitdone(priv) < 0) {
		status = imxrt_lpi2c_getstatus(priv);
		ret = -ETIMEDOUT;

		i2cerr("ERROR: Timed out: MCR: status: 0x%x\n", status);
	}

	/* Check for error status conditions */

	if ((status & LPI2C_MSR_ERROR_MASK) != 0) {
		/* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */

		if (status & LPI2C_MSR_BBF(1U)) {
			/* Bus Error */

			ret = -EIO;
		} else if (status & LPI2C_MSR_ALF(1U)) {
			/* Arbitration Lost (master mode) */

			ret = -EAGAIN;
		} else if (status & LPI2C_MSR_NDF(1U)) {
			/* Acknowledge Failure */

			ret = -ENXIO;
		} else {
			ret = -EINTR;
		}
	}

	/* Dump the trace result */

	imxrt_lpi2c_tracedump(priv);

	/* Ensure that any ISR happening after we finish can't overwrite any user data */

	priv->dcnt = 0;
	priv->ptr = NULL;

	imxrt_lpi2c_sem_post(priv);
	return ret;
}
#endif

/************************************************************************************
 * Public Functions
 ************************************************************************************/

/************************************************************************************
 * Name: up_i2cinitialize
 *
 * Description:
 *   Initialize one I2C bus
 *
 ************************************************************************************/

FAR struct i2c_dev_s *up_i2cinitialize(int port)
{
	struct imxrt_lpi2c_priv_s *priv = NULL;
	irqstate_t flags;

	/* Get I2C private structure */

	switch (port) {
#ifdef CONFIG_IMXRT_LPI2C1
	case 1:
		priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c1_priv;
		break;
#endif
#ifdef CONFIG_IMXRT_LPI2C2
	case 2:
		priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c2_priv;
		break;
#endif
#ifdef CONFIG_IMXRT_LPI2C3
	case 3:
		priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c3_priv;
		break;
#endif
#ifdef CONFIG_IMXRT_LPI2C4
	case 4:
		priv = (struct imxrt_lpi2c_priv_s *)&imxrt_lpi2c4_priv;
		break;
#endif
	default:
		return NULL;
	}

	/* Initialize private data for the first time, increment reference count,
	 * power-up hardware and configure GPIOs.
	 */

	flags = irqsave();

	if ((volatile int)priv->refs++ == 0) {
		imxrt_lpi2c_sem_init(priv);
		imxrt_lpi2c_init(priv);
	}

	irqrestore(flags);

	return (struct i2c_dev_s *)priv;
}

/************************************************************************************
 * Name: up_i2cuninitialize
 *
 * Description:
 *   Uninitialize an I2C bus
 *
 ************************************************************************************/

int up_i2cuninitialize(FAR struct i2c_dev_s *dev)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (struct imxrt_lpi2c_priv_s *)dev;
	irqstate_t flags;

	DEBUGASSERT(dev);

	/* Decrement reference count and check for underflow */

	if (priv->refs == 0) {
		return ERROR;
	}

	flags = irqsave();

	if (--priv->refs > 0) {
		irqrestore(flags);
		return OK;
	}

	irqrestore(flags);

	/* Disable power and other HW resource (GPIO's) */

	imxrt_lpi2c_deinit(priv);

	/* Release unused resources */

	imxrt_lpi2c_sem_destroy(priv);
	return OK;
}

/************************************************************************************
 * Name: up_i2creset
 *
 * Description:
 *   Reset an I2C bus
 *
 ************************************************************************************/

#ifdef CONFIG_I2C_RESET
int up_i2creset(FAR struct i2c_dev_s *dev)
{
	FAR struct imxrt_lpi2c_priv_s *priv = (FAR struct imxrt_lpi2c_priv_s *)dev;
	unsigned int clock_count;
	unsigned int stretch_count;
	uint32_t scl_gpio;
	uint32_t sda_gpio;
	uint32_t frequency;
	int ret = ERROR;

	DEBUGASSERT(dev);

	/* Our caller must own a ref */

	DEBUGASSERT(priv->refs > 0);

	/* Lock out other clients */

	imxrt_lpi2c_sem_wait(priv);

	/* Save the current frequency */

	frequency = priv->frequency;

	/* De-init the port */

	imxrt_lpi2c_deinit(priv);

	/* Use GPIO configuration to un-wedge the bus */

	scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
	sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);

	imxrt_config_gpio(scl_gpio);
	imxrt_config_gpio(sda_gpio);

	/* Let SDA go high */

	imxrt_gpio_write(sda_gpio, 1);

	/* Clock the bus until any slaves currently driving it let it go. */

	clock_count = 0;
	while (!imxrt_gpio_read(sda_gpio)) {
		/* Give up if we have tried too hard */

		if (clock_count++ > 10) {
			goto out;
		}

		/* Sniff to make sure that clock stretching has finished.
		 *
		 * If the bus never relaxes, the reset has failed.
		 */

		stretch_count = 0;
		while (!imxrt_gpio_read(scl_gpio)) {
			/* Give up if we have tried too hard */

			if (stretch_count++ > 10) {
				goto out;
			}

			up_udelay(10);
		}

		/* Drive SCL low */

		imxrt_gpio_write(scl_gpio, 0);
		up_udelay(10);

		/* Drive SCL high again */

		imxrt_gpio_write(scl_gpio, 1);
		up_udelay(10);
	}

	/* Generate a start followed by a stop to reset slave
	 * state machines.
	 */

	imxrt_gpio_write(sda_gpio, 0);
	up_udelay(10);
	imxrt_gpio_write(scl_gpio, 0);
	up_udelay(10);
	imxrt_gpio_write(scl_gpio, 1);
	up_udelay(10);
	imxrt_gpio_write(sda_gpio, 1);
	up_udelay(10);

	/* Revert the GPIO configuration. */

	sda_gpio = MKI2C_INPUT(sda_gpio);
	scl_gpio = MKI2C_INPUT(scl_gpio);

	imxrt_config_gpio(sda_gpio);
	imxrt_config_gpio(scl_gpio);

	/* Re-init the port */

	imxrt_lpi2c_init(priv);

	/* Restore the frequency */

	imxrt_lpi2c_setclock(priv, frequency);
	ret = OK;

out:

	/* Release the port for re-use by other clients */

	imxrt_lpi2c_sem_post(priv);
	return ret;
}
#endif							/* CONFIG_I2C_RESET */

#endif							/* CONFIG_IMXRT_LPI2C1 || CONFIG_IMXRT_LPI2C2 || \
								 * CONFIG_IMXRT_LPI2C3 || CONFIG_IMXRT_LPI2C4 */
